The W5500 chip is an embedded Ethernet controller that facilitates hardwired network connections for embedded systems via SPI (Serial Peripheral Interface). This chip is particularly useful for users requiring stable internet connectivity, as it integrates TCP/IP Stack, 10/100 Ethernet MAC and PHY into a single chip. The W5500 chip supports various protocols such as TCP, UDP, IPv4, ICMP, ARP, IGMP, and PPPoE, which have been widely used in many applications.
The W5500 also features a 32Kbytes internal buffer as its data communication memory, making it easy for users to implement Ethernet applications using simple socket programming instead of dealing with complex Ethernet controllers. The chip supports 8 independent hardware sockets and an efficient SPI protocol, allowing for high-speed network communication at 80 MHz. Additionally, the W5500 includes power-saving features such as Wake on LAN (WOL) and a power-down mode.
Note: While this device can be used with an ESP32 over the SPI Bus, it is not compatible with the builtin hardware Ethernet MAC that exists in the ESP32.
- Supports following Hardwired TCP/IP Protocols : TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE
- Supports 8 independent sockets simultaneously
- Supports Power down mode
- Supports Wake on LAN over UDP
- Supports High Speed Serial Peripheral Interface(SPI MODE 0, 3)
- Internal 32Kbytes Memory for Tx/Rx Buffers
- 10BaseT/100BaseTX Ethernet PHY embedded
- Support Auto Negotiation (Full and half duplex, 10 and 100-based)
- Not support IP Fragmentation
- 3.3V operation with 5V I/O signal tolerance
- LED outputs (Full/Half duplex, Link, Speed, Active)
- Chipset: W5500
- Module size: 55mm x 28mm
- Power supply: 3.3v /5v
- SPI clock frequency(MAX): 80MHz
- Work current(typical): 128mA
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